STA310 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA310' PDF : 90 Pages View PDF
STA310
Description:
This register indicates the status of the audio parser
for synchronization. It is used in conjunction with
PACKET_LOCK and SYNCK_LOCK registers. On
read the synchronization status interrupt bit is
cleared (INT.SYN is cleared).
Bitfield
Description
FRA
Frame Status
0 0: Research audio synchronization
0 1: Wait for confirmation - a synchro word has
been detected but the parser has not yet
detected SYNC-LOCK+1 synchro words.
1 0: Synchronized - SYNC_LOCK + 1 synchro
words have been detected
1 1: Not used
PAC
Packet Status
0 0: Research packet synchronization word
0 1: Wait for confirmation - - a synchro word
has been detected but the parser has not yet
detected
PACKET_LOCK+1 synchro words.
1 0: Synchronized - PACKET_LOCK + 1
synchro words have been detected
1 1: Not used
ANCCOUNT
Ancillary data
7
6 54
3
2
1
0
Address: 0x41
Type: RO
Software Reset: UND
Hardware Reset: UND
Description:
This value gives the number of ancillary data in the
stream. The ancillary data interrupt bit ANC of the
register is cleared by a read.
HEAD4
HEADER 4 register
AC_3
76543 2
1
0
00000
BSMOD
MPEG_2
00000
0
DR
K
OTHER
0
0
0
0
0
000
Address: 0x42
Type: RO
Software Reset: UND
Hardware Reset: UND
Description:
This register contains header data HEAD[31:24]. The
contents depend on the type of the
frame.HEAD4[7:3] = 00000, in all cases.
When the host reads this register, the corresponding
interrupt bit (HDR) is cleared.
Dolby Digital
Bitfield
Description
HEAD4[2:0] BSMOD if an Dolby Digital frame
MPEG-2
Bitfield
HEAD4[2]
HEAD4[1]
HEAD4[0]
Description
0
DR=1 Dynamic range exists
K=0 in normal mode, K=1 in Karaoke
mode.
OTHER
In all other types of frame HEAD4[2:0] = “000”
HEAD3
HEADER 3 register
7
6
5 4321
0
0
0
0
DTYPE
Address: 0x43
Type: RO
Software Reset: UND
Hardware Reset: UND
Description:
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