STA310 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA310' PDF : 90 Pages View PDF
STA310
Address: 0x56
Type: R/W
Software Reset: NC
Hardware Reset: UND
Fs
(KHz)
46
44.1
32
-
96 88.2 64
-
24 22.05
Value 0 1 2 3 4 5 6 7 8 9
Description:
The PCMCROSS register only acts if bit PFC of reg-
ister SPDIF_DTDI is set.
Bitfield
Description
LRS[1:0] Cross left and right surround.
CSW[1:0] Cross centre and subwoofer.
CLR[1:0]
Cross left and right channels.
00: Left channel is mapped on the left
output, Right channel is mapped on the
Right output.
01: Left channel is duplicated on both
outputs.
10: Right channel is duplicated on both
outputs.
11: Right channel and Left channel are
toggled.
VCR[1:0] These 2 bits manage the VCR outputs.
9.6 PDAC and PLL configuration registers
SFREQ
Sampling frequency
7
6
5
4
3
2
1
0
Address: 0x05
Type: R/WS
Software Reset: NC
Hardware Reset: 0
Description:
This status register holds the code of the current
sampling frequency. If the audio stream is encoded
(Dolby Digital, MPEG) or packetized (DVD_LPCM),
the sampling frequency is automatically read in the
audio stream and written into this register by the au-
dio DSP. The register is automatically updated by the
DSP when it performs a down-sampling (for exam-
ple, 96kHz to 48kHz).
The DSP resets SFREQ to 0.
For PCM stream or CDDA, this register is written to
by the application. The value in SFREQ corresponds
to the following frequencies:.
Fs
(KHz)
16
-
12 11.025
8
- 192 176.4 128 -
Value 10 11 12 13 14 15 16 17 18 19
PLLCTRL
PLL Control
765
4
3
SYSCLSCK[1..0]
Address: 0x12
Type: R/W
Software Reset: NA
Hardware Reset: 0x19
210
OCLK[2..0]
Description:
Bitfield Value Description
OCLK
[2:0]
Configure PCMCLK PCMCLK pad
source and direction direction
-01 Audio master Clock Input
from PCMLCK pad.
011 Audio master Clock Input
from internal audio
PLL
111 Audio master Clock Input
from internal S/PDIF
receiver
-00 Forbidden
010 Audio master Clock Output
from internal audio
PLL
110 Audio master Clock Output
from internal S/PDIF
receiver
SYSCLC 0
K[1:0]
System Clock from CLK pad
Output
1
System Clock from CLK pad divided
by 2
2
System Clock from internal system
PLL
3
System Clock from internal system
PLL divided by 2
PLL_DATA
41/90
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