STA310 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA310' PDF : 90 Pages View PDF
STA310
RVDLY
Right VCR channel delay
Software Reset: 0
Hardware Reset 0
7
6
5
4
3
2
1
0
Description:
Address: 0xB0
Type: R/W
Software Reset: NC
Hardware Reset: UND
Description:
Delay on right VCR channel, expressed in number of
group of 16 samples. RSDLY = delay (ms) * Fs (kHz)
/ 16.
When only one VCR channel is used, this register
must be reset at initialization.
Bitfield
Description
DLY
This bit must be set to 1 to force the DSP to
update its delays values (read from the audio
delay registers).
0: Delay values held in the audio delay
registers are NOT updated in the DSP
(i.e. the DSP will keep the delay values set
previously)
1: The delay values held in the audio delay
registers are updated in the DSP (i.e. the
DSP will use the new values). This bit is
automatically reset to zero after it the update
has been carried out.
UPDATE
PCM delay update
TM
Set to “0”
7
6
5
4
3
2
1
0
TM DLY
Address: 0x5D
Type: R/W
9.8 SPDIF output set-up
SPDIF_CMD
SPDIF control
7
6
5
4
3
2
1
0
AUX
reserved
SPDIF_MODE[1:0]
Address: 0x5E
Type: R/W
Software Reset: NC
Hardware Reset: UND
Bitfield
This register controls the SPDIF mode:
Description:
Description
SPDIF_MODE[1:0]
AUX = ’0’
00: OFF, the IEC60958 is not working and the output line is idle,
01: MUTE, the outputs are PCM null data,
10: PCM, the outputs are PCM data and only the Left/Right channels are transmitted,
11: EMC, in this "encoded" mode the compressed bitstream is transmitted in IEC61937
standard.
SPDIF_MODE[1:0] 10: PCM, the outputs are PCM data and only the "VCR" channels are transmitted.
AUX = ’1’
All other values are reserved.
SPDIF_CAT
Category code
7
6
5
4
3
2
1
0
CATCODE
47/90
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