STA310 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA310' PDF : 90 Pages View PDF
STA310
PLLData
7
6
5
4
3
2
1
0
Address: 0x11
Type: R/W
Software Reset: NA
Hardware Reset: 0
Description:
Data that must be written (has been read) at (from)
the address specified by PLL_ADD.
PLL_CMD
PLL Command
7654
3
2
10
AUPLLCTL SYSPLLCTL RWCTL[1:0]
Address: 0x1D
Type: R/W
Software Reset: NA
Hardware Reset: 0
PLL Address
7
6
5
4
3
2
1
0
ADDRESS
Address: 0x12
Type: R/W
Software Reset: NA
Hardware Reset: 0
Description:
Value Address of PLLs configuration registers
Address
2: Disable System PLL
3: System PLL frac Low
4: System PLL frac High
6: System PLL N divider
7: System PLL X divider
8: System PLL M divider
9: System PLL update
10: Disable Audio PLL
11: Audio PLL Frac Low
12: Audio PLL Frac High
14: Audio PLL N divider
15: Audio PLL X divider
16: Audio PLL M divider
17: udio PLL update
Description:
Bitfield
Description
RWCTL [1:0]
Configure PCMCLK source and
direction.
00: No action is performed on the
configuration registers of the level 1
01: Read action of the configuration
registers. During this phase, the
content of a selectable (by PLL_ADD)
register of the level 1 is copied into the
PLL_DATA register.
10: Write action of the configuration
registers. During .this phase, the
content of a selectable (by PLL_ADD)
register of the level 1 is copied into the
PLL_DATA register.
11: Forbidden
SYSPLLCTL
System PLL coefficients transfert
0: No Transfer
1: Transfer the data between the level 1
and the level 2 for the system PLL
AUPLLCTL
Audio PLL coefficient transfert
0: No Transfer
1: Transfer the data between the level 1
and the level 2 for the audio PLL
PLL_ADD
ENA_AU_FRACPLL
Audio PLL Enable
7 6 54 3 21
0
ENA_PLL
Address: 0xB5
Type: R/W
Software Reset: 1
Hardware Reset: 0
Description:
This register is used to enable the audio PLL of the
STA310. This register must be always set to “1” after
either a soft or hardware reset.
AU_PLL_FRACL_192
Frac Low Coefficient
7
6
5
4
3
2
1
0
FRACL
Address: 0xB6
42/90
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