STA310 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA310' PDF : 90 Pages View PDF
STA310
384 x SF (where SF is the sampling frequency)
– External crystal provide a clock running at
27MHz
AU_PLL_FRACL_176
Frac Low Coefficient
7
6
5
4
3
2
1
0
FRACL
Address: 0xBB
Type: R/W
Software Reset: 0x3
Hardware Reset: UND
Description:
This register must contain a FRACL value that en-
ables the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume:
– Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency)
– External crystal provide a clock running at
27MHz
AU_PLL_FRACH_176
Frac High Coefficient
7
6
5
4
3
2
1
0
FRACH
Address: 0xBC
Type: R/W
Software Reset: 0x9
Hardware Reset: UND
Description:
This register must contain a FRACH value that en-
ables the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume:
– Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency)
– External crystal provide a clock running at
27MHz
AU_PLL_XDIV_176
X Divider Coefficient
7
6
5
4
3
2
1
0
XDIV
Address: 0xBD
Type: R/W
Software Reset: 0x01
Hardware Reset: UND
Description:
This register must contain a XDIV value that enables
the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume:
– Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency)
– External crystal provide a clock running at
27MHz
AU_PLL_MDIV_176
M Divider Coefficient
7
6
5
4
3
2
1
0
MDIV
Address: 0xBE
Type: R/W
Software Reset: 0x09
Hardware Reset: UND
Description:
This register must contain a MDIV value that enables
the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume:
– Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency)
– External crystal provide a clock running at
27MHz
AU_PLL_NDIV_176
N Divider Coefficient
7
6
5
4
3
2
1
0
NDIV
44/90
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