STA310 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA310' PDF : 90 Pages View PDF
STA310
3.2 Functional diagram
Figure 2. Audio decoder top level functional diagram
SSTTAA33110 0
DCSB 21
IRQ 48
SDAI2C 43
SCLKI2C 46
MAINI2CADR 53
CONTROL
A[0..7]
D[0..7]
SIN 41
LRCLKIN 40
DSTRB 37
REQ 42
I2S_IN1
SIN2 60
LRCLKIN2 61
DSTRB2 62
REQ2 63
I2S_IN2
FRAME
BUFFER
PACKET
FORMATTER PTS
Voice Effects:
Echo,
Chorus
Reverb
Pink Noise Gen
Beep Tone Gen
MP3
LPCM
video
PCM
CDDA
MPEG 1
Layer 1-2
AC-3
MPEG 2
IEC 1937 (AC-3 / MPEG 2)
NULL DATA
6
2
PCM
Switctch
L/Lt
1..4 L
2
2
R/Rt
2
R
C
C
Lfe
lfe
6
Ls
6
6
1..6 Ls
Rs
Rs
L DELAY
R DELAY
C DELAY
lfe DELAY
Ls DELAY
Rs
DELAY
Sample
Rate
Converter
MLP
Gain
Level Sensitive
Cancel
2 to 6 ch
Downmix Lt/Rt
2/0
2to2
6to2
2
LVCR DELAY
RVCR DELAY
System
and
Audio
Clocks
58 I958OUT
73 PCMOUT1
76 PCMOUT2
77 PCMOUT3
72 PCMOUT0
63 SCLK
68 LRCLK
64 CLKOUT
31 CLK
69 PCMCLK
3.3 Control interface description
The IC can be controlled either by a host using an I²C interface, or by a general purpose host interface.
These interfaces provide the same functions and are described in the following sections. The selection is per-
formed by the means of the pin SELI2C: when high, this pin indicates that the I²C interface is used. When low,
the parallel interface is used.
3.3.1 Parallel control interface
When the pin SELI2C is low, the control of the chip is performed through the parallel interface. When accessing
the device through the parallel interface, the following signals are used:
- The address bus A[7..0]. It is used to select one of the 256 register locations.
- The data bus DATA[7..0]. If a read cycle is requested, the data lines D[7:0] will be driven by the IC.
For a write cycle, the STA310 will latch the data placed on the data lines when the WAIT signal is
driven high.
- The signal R/W. It defines the type of register access: either read (when high), or write (when low).
Some registers can be either written or read, some are read only, some are write only.
- The signal DCSB. A cycle is defined by the assertion of the signal DCSB.
Note: 1. The address bus A[7..0], and read/write signal R/W must be setup before the DCSB line is activated.
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