Register description
STA339BW
Table 73. RAM block for biquads, mixing, scaling and bass management (continued)
Index (decimal) Index (hex)
RAM block setting
Coefficient
Default
55
0x37
TWARN/OC - Limit
TWOCL
0x5A9DF7
56
0x38
Channel 1 - Mix 1
C1MX1
0x7FFFFF
57
0x39
Channel 1 - Mix 2
58
0x3A
Channel 2 - Mix 1
C1MX2
C2MX1
0x000000
0x000000
59
0x3B
Channel 2 - Mix 2
C2MX2
0x7FFFFF
60
0x3C
Channel 3 - Mix 1
C3MX1
0x400000
61
0x3D
Channel 3 - Mix 2
C3MX2
0x400000
62
0x3E
Unused
63
0x3F
Unused
-
-
-
-
7.13
Variable max power correction registers (addr 0x27 - 0x28)
D7
MPCC15
0
D6
MPCC14
0
D5
MPCC13
0
D4
MPCC12
1
D3
MPCC11
1
D2
MPCC10
0
D1
MPCC9
1
D0
MPCC8
0
D7
MPCC7
1
D6
MPCC6
1
D5
MPCC5
0
D4
MPCC4
0
D3
MPCC3
0
D2
MPCC2
0
D1
MPCC1
0
D0
MPCC0
0
MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is
used in place of the default coefficient when MPCV = 1.
7.14
Variable distortion compensation registers (addr 0x29 -
0x2A)
D7
DCC15
1
D6
DCC14
1
D5
DCC13
1
D4
DCC12
1
D3
DCC11
0
D2
DCC10
0
D1
DCC9
1
D0
DCC8
1
D7
DCC7
0
D6
DCC6
0
D5
DCC5
1
D4
DCC4
1
D3
DCC3
0
D2
DCC2
0
D1
DCC1
1
D0
DCC0
1
DCC bits determine the 16 MSBs of the Distortion compensation coefficient. This coefficient
is used in place of the default coefficient when DCCV = 1.
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