STA3398 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STA3398
STMicroelectronics
'STA3398' PDF : 78 Pages View PDF
Register description
STA339BW
7.17 EQ coefficients and DRC configuration register (addr 0x31)
D7
XOB
0
D6
D5
Reserved
0
0
D4
AMGC[3]
0
D3
AMGC[2]
0
D2
Reserved
0
D1
SEL[1]
0
SEL[1:0]
Table 75. EQ RAM select
EQ RAM bank selected
00/11
01
10
Bank 0 activated
Bank 1 activated
Bank 2 activated
D0
SEL[0]
0
Bits AMGC[3:2] change the behavior of the bits AMGC[1:0] as given in Table 76 below.
AMGC[3:2]
00
01
10/11
Table 76. Anti-clipping and DRC preset
Anti-clipping and DRC preset selected
DRC/Anti-clipping behavior described in Table 56 on page 48 (default).
DRC/Anti-clipping behavior is described in Table 77 below
Reserved, do not use
When AMGC[3:2] = 01 then the bits 1:0 are defined as given here in Table 77.
Table 77. Anti-clipping selection for AMGC[3:2] = 01
AMGC[1:0]
Mode
00
AC0, stereo anticlipping 0 dB limiter
01
AC1, stereo anticlipping +1.25 dB limiter
10
AC2, stereo anticlipping +2 dB limiter
11
Reserved do not use
AC0, AC1, AC2 settings are designed for the loudspeaker protection function, limiting at the
minimum any audio artefacts introduced by typical anti-clipping/DRC algorithms. More
detailed information is available in the applications notes “Configurable output power rate
using STA335BW” and “STA335BWS vs STA335BW”.
Bit XOB can be used to bypass the crossover filters. Logic 1 means that the function is not
active. In this case, high pass crossover filter works as a passtrough on the data path
(b0 = 1, all the other coefficients at logic 0) while the low pass filter is configured to have
zero signal on channel-3 data processing (all the coefficients are at logic 0).
66/78
DocID15251 Rev 7
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