CONFIDENTIAL STi5512
External memory interface
Pin
MemAddr2-23
MemData0-31
In/Out
out
in/out
Function
Address bus.
Data bus. MemData0 is the least significant bit (LSB) and MemData31 is the most
significant bit (MSB).
MemRdnotWr
out
ReadnotWrite strobe.
MemReq
in
Direct memory access request.
MemGrant
out
Direct memory access granted.
MemWait
in
Memory cycle extender.
notMemCAS0,2
out
CAS strobes for SDRAM/DRAM in Banks 0 and 1
notMemCAS1
out
CAS strobe for DRAM or SDRAM clock
notMemCAS3
out
CAS strobe for DRAM or sub-bank chip select for bank 3.
notMemRAS0
out
RAS strobe for SDRAM/DRAM in Bank 0, chip select for Bank0 or
notMemRAS1
RAS strobe for lowest DRAM sub-bank in Bank0
out
RAS strobe for highest DRAM sub-bank in Bank0 or
notMemRAS2
SDRAM Chip select signal for highest sub-bank of Bank0
out
RAS strobe for SDRAM/DRAM in bank 1, chip select for Bank1 or
notMemRAS3
RAS strobe for lowest DRAM sub-bank in Bank1
out
RAS strobe for highest DRAM sub-bank in Bank1 or
notSDRAMCS0
notMemCSROM
notMemOE
notMemBE0-3
SDRAM Chip select signal for Bank1
out
SDRAM Chip select signal for Bank0 or lowest sub-bank of Bank0
out
Chip select strobe for bank3 or highest sub-bank in Bank3
out
Output enable strobe - banks 0-3.
out
Byte enable strobes - banks 0-3.
notMemCS2
BootSource0-1
ProcClockOut
DQM signals for SDRAM
out
Chip select strobe for memory in bank 2.
in
Boot from ROM or from link.
out
Processor clock
Table 6 STi5512 external memory pins
Shared SDRAM interface
Pin
AD0-12
DQ0-15
notSDCS0
notSDCS1/AD13
notSDCAS
notSDRAS
notSDWE
MEMCLKIN
MEMCLKOUT
DQML
DQMU
In/Out
out
in/out
out
out
out
out
out
in
out
out
out
Function
SDRAM address bus.
SDRAM data bus (lower byte).
SDRAM chip select for first SDRAM
SDRAM chip select for second SDRAM or AD13
SDRAM CAS.
SDRAM RAS.
SDRAM write enable.
SDRAM memory clock input.
SDRAM memory clock output.
DQ mask enable (lower).
DQ mask enable (upper).
Table 7 Shared SDRAM interface pins
7110123 B
15//23