STI5512 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STI5512' PDF : 23 Pages View PDF
CONFIDENTIAL STi5512
2.1 STi5512 functional modules
STi5512 architecture block diagram on page 6 shows the subsystem modules that comprise the STi5512. These
modules are outlined below.
Processor
The Central Processing Unit (CPU) on the STi5512 is the enhanced ST20-C2 32-bit processor core running at 60 MHz
clock rate. It contains instruction processing logic, instruction and data pointers, and an operand register. It directly
accesses the high speed on-chip caches and SRAM, which can store data or programs. The processor can also access
memory via the External Memory Interface (EMI) and SDRAM interface.
MPEG-2 video and MPEG-1 audio decoder subsystems
This subsystem takes the MPEG compressed data streams and decompresses them, outputting digital YUV data in the
case of the video decoder, and stereo PCM samples in the case of the audio decoder. The decoded video is fed to the
display subsystem. An interface is provided to output an audio bit-stream for decoding by an external MPEG or AC-3
decoder to support multi-channel (surround) audio.
The video decoder implemented on the STi5512 uses a patented memory reduction/bandwidth reduction scheme to
offer the user the best compromise between bandwidth and memory size. The algorithm is lossless and uses “on-the-
fly” decoding to reduce the memory requirements to two frame buffers in memory size reduction mode. When used in
bandwidth reduction mode, the memory usage is the normal three buffers, but the bandwidth required by the decoder
is significantly reduced over a classical implementation.
Background
color
Still
picture
France plane
Decompressed
video
France
08:23pm
Replay Score Stats
08:23pm
Replay Score Stats
On-screen display
Cursor on sub-picture plane
Sub-picture optional
positions
08:23pm
France
Replay Score Stats
Figure 3 Display planes
The SDRAM interface includes all the signals necessary for control of the memory. Refresh is handled automatically by
the decoder. The SDRAM interface supports two 16-Mbit or one 64-Mbit 100 MHz SDRAMs. The memory is used to
hold the bit buffer, store decoded pictures and provide the display buffer. It also holds the user-defined on-screen
display (OSD) bitmaps and can be used by the CPU for private storage of data. For the decoding of PAL MP@ML
sequences, 12 Mbits of SDRAM are required.
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