STLC1502 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC1502' PDF : 81 Pages View PDF
STLC1502
NAME
EDM_RAS
EDM_CAS
OEN
Signal type
OUT
OUT
OUT
EDM_WE
EDM_BS(3:0)
OUT
OUT
EDM_A(21::0) OUT
EDM_D(31:0) INOUT
Description
SDRAM RAS signal. Not used with EDO.
SDRAM CAS signal. Not used with EDO
SRAM Output Enable. Not used with
SDRAM
DRAM Write Enable
SDRAM byte strobe. CAS when EDO memo-
ries are used
DRAM address lines, only 14 lines are
driven.. Lines.21:14 are driven by static
memory controller
DRAM data lines, shared with static memory
controller lines.
The EDM block includes a decoder in order to generate proper CS to the external device. In particular this de-
coder will work on bits 25 and 26 of internal ARM address bus.
EDM
Decoder
EDM_A(13:0)
EDM decoding scheme
• Every CS space can be programmed through internal register in order to configure the EDM to work
with the proper external device
• The DRAM Controller has nine registers, the configuration register, four bank registers and four
SDRAM configuration registers. The registers are accesses via the APB bus. The register data path
is 16 bits wide.
6.3.1 EDM Register Map [0x0C580000]
• The base address of the EDM register is 0x0C580000
Address
EDMBase +
0x00
EDMBase +
0x04
Register
Name
MB1Config
R/W Notes
R/W Memory Bank 1 Configuration Register
MB2Config R/W Memory Bank 2 Configuration Register
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