STLC1502 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC1502' PDF : 81 Pages View PDF
STLC1502
• Defines the data width of the external memory device:
• 00 - Byte (8 bit)
• 01 - Half Word (16 bit)
• 10 - Word (32 bit)
DATALAT: Data Latency
• Defines the number of memory clock cycles between the start of a memory read access and the first
valid data.
• The DATALAT value is valid between 0 and 3.
SETUPTIME: Setup Time
• Defines the number of memory clock cycles the memory driver spends in the DECODE state before
accessing the external memory.
• The SETUPTIME value is valid between 0 and 7.
IDLETIME: Idle Time
• Defines the minimum time the memory driver must spend in the IDLE state following memory
accesses.
• The value defines the number of Memory Clock cycles.
• The IDLETIME value is valid between 0 and 7.
SDRAMCOL: SDRAM Column Width Definition
• Specifies the width of the SDRAM column address:
• 00 - 8 bits
• 01 - 9 bits
• 10 - 10 bits
• 11 - reserved
6.3.1.2 SDRAM Configuration registers
These registers are write only. A write access to the high registers will start the SDRAM configuration cycle,
during which the value written to the register will be asserted on the memory bus for a one clock period.
Low SDRAM Configuration Registers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
MIAB
MIAB: Memory Interface Address Bus
High SDRAM Configuration Registers
15 14 13 12 11 10 9 8
Reserved
765432
1
0
MIVE MIAA MISA
19/81
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