STLC5046 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC5046' PDF : 27 Pages View PDF
STLC5046
REGISTERS DESCRIPTION
Configuration Register (CONF)
Addr=00h; Reset Value=3Fh
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RES LIN AMU STA PD3 PD2 PD1 PD0
RES=0Normal Operation
RES=1 Device Reset: I/0n and CSn are all inputs,
DX is H.I. (equivalent to Hw. reset).
LIN=0 A or µ law PCM encoding
LIN=1 Linear encoding (16 bits), two’s comple-
ment.
AMU=0µ law selection
AMU=1 A law selection (even bits inverted)
STA=0 CS0 to CS3 scan the four SLICs con-
nected to the I/O control port, each CS has a
31.25µs repetition time.
STA=1; I/O are static, CS0 to CS3 are config-
ured as generic static I/O
PD3..0=0 Codec 3..0 is active
PD3..0=1 Codec 3..0 is in power Down. When
one codec is in Power Down the corresponding
VFRO output is forced to AGND. and the corre-
sponding transmit time slot on DX is set in H.I.
Pin strap value:
RES 0 AMU 0 PD3 PD2 PD1 PD0
I/O Direction Register (DIR)
Addr=01h; Reset Value=00h
Addr=02h; Reset Value=X0h
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
IO11 IO10 IO9 IO8
IO11..0 = 0; I/O pin 11..0 is an input, data on the
I/O input is written in DATAn register bit 11..0.
IO11..0 = 1; I/O pin 11..0 is an output, data con-
tained in DATAn register bit11..0 is transferred to
the I/O output.
Pin strap value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I/O Data Register channel #0 (DATA0)
Addr=03h; Reset Value=00h
Addr=04h; Reset Value=X0h
If bit 4 of CONF register (STA)=0
Dynamic I/O mode:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
D07 D06 D05 D04 D03 D02 D01 D00
D011 D010 D09 D08
When CS0 is active D011..0 are transferred to the
corresponding I/O pins configured as outputs
(see DIR register). For the I/O pins configured as
inputs the corresponding D011..0 will be written by
the values applied to those pins while CS0 is low.
If bit 4 of CONF register (STA)=1
Static I/O mode:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS0
DS11 DS10 DS9 DS8
D11..0 are transferred to the corresponding I/O
pins configured as outputs (see DIR register). For
the I/O pins configured as inputs the correspond-
ing D11..0 will be written by the values applied to
those pins.
Pin strap value:
0
0
0
0
0
0
0
0
0
0
0
0
I/O Data Register channel #1 (DATA1)
Addr=05h; Reset Value=00h
Addr=06h; Reset Value=X0h
If bit 4 of CONF register (STA)=0
Dynamic I/O mode:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
D17 D16 D15 D14 D13 D12 D11 D10
D111 D110 D19 D18
When CS1 is active D11..0 are transferred to the
corresponding I/O pins configured as outputs
(see DIR register). For the I/O pins configured as
inputs the corresponding D11..0 will be written by
the values applied to those pins while CS1 is low.
If bit 4 of CONF register (STA)=1
11/27
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