STLC5046 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC5046' PDF : 27 Pages View PDF
STLC5046
Figure 6c. MCU Mode Frame Sync. Timing.
MCLK
FS
DX
DR
TSX
tHMF
1
2
tSFM
tRM
tFM
3
4
5
tWMH
6
7
tWML
tDMD
1
1
2
3
4
tSDM tHMD
2
3
4
5
5
6
7
6
7
16
17
tDMZ
16
16
tXDP
D98TL388C
tDZC
ELECTRICAL CHARACTERISTICS (continued)
SERIAL CONTROL PORT TIMING
Symbol
fCCLK
tWCH
tWCL
tRC
tFC
tHCS
tSSC
tSDC
tHCD
tDCD
tDSD
tDDZ(1)
tHSC
tSCS
Parameter
Test Condition
Frequency of CCLK
Period of CCLK high
Measured from VIH to VIH
Period of CCLK low
Measured from VIL to VIL
Rise Time of CCLK
Measured from VIL to VIH
Fall Time of CCLK
Measured from VIH to VIL
Hold Time, CCLK high to CS– low
Setup Time, CS– low to CCLK high
Setup Time, CI valid to CCLK high
Hold Time, CCLK high to CI
invalid
Delay Time, CCLK low to CO
data valid
Delay Time, CS–low to CO data
valid
Delay Time CS–high or 8th
CCLK low to CO high impedance
whichever comes first
Hold Time, 8th CCLK high to
CS– high
Setup Time, CS– high toCCLK high
Pull up resistor = 1kΩ
Cload = 30pF
(1) It is defined as the time at which the output achivies the off state.
22/27
Min.
100
100
5
10
20
10
Typ.
10
Max.
4.096
20
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
30
ns
20
ns
50
ns
10
ns
10
ns
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