STLC5046
Figure 7. Serial control port timing.
CCLK
tHCS
CS-
CO
1
2
tSSC
tRC
tFC
3
4
5
6
BYTE 1
tSDC
tWCH
7
8
1
2
3
4
5
6
tHCS
tWCL
tHCS
tSCS
tSCS
te
tHCD
tDSD
BYTE 2
tDCD
7
8
tHSC
tDDZ
7
6
5
4
3
2
1
0
CI
7
6
5
4
3
2
1
0
D99TL454
ELECTRICAL CHARACTERISTICS (continued)
SLIC CONTROL INTERFACE TIMING
Symbol
TCS
tcsw
tDIV
tDII
tDOA
tDON
Parameter
Test Condition
Chip Select repetition rate
Chip select pulse width
Time CS low to data input valid
Time data input invalid to CS high
Time data output available to CS low
Time CS high to data output not available
Figure 8. SLIC Control port timing.
Min. Typ. Max. Unit
31.25
µs
3.90
µs
1.65
µs
1.65
µs
1.8
µs
1.8
µs
tDIV tDII
tDOA
tDON
CS1
31.25µs (32KHz)
CS2
CS3
CS4
IO
(OUT)
IO
(IN)
OUT
CH0
IN
CH0
OUT
CH1
IN
CH1
OUT
CH2
IN
CH2
OUT
CH3
IN
CH3
OUT
CH0
IN
CH0
OUT
CH1
IN
CH1
D99TL460
23/27