STLC60134S View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC60134S' PDF : 22 Pages View PDF
STLC60134S
Control Interface Timing
The word clock (CLWD) is used to sample at negative going edge the control information. The start bit b15
is transmitted first followed by bits b[14:0] and at least 16 stop bits need to be provided to validate the data.
Figure 12. Control Interface.
CLWD
CTRLIN
START
BIT
D98TL365
DATA
ID.
>=16 STOP BITS=HIGH
Data set-up and hold time versus falling edge CLWD must be greater than 10nsec.
Receive / Transmit Interface
RECEIVE / TRANSMIT PROTOCOL
The digital interface is based on 4 x 8.832MHz (35.328MHz) data lines in the following manner:
If OSR = 2 (OSR bit set to 1) is selected, CLKNIB is used as nibble clock (17.664MHz, disabled in normal
mode), and all the RXi, TXi, CLKWD periods are twice as long as in normal mode. This ensures a compati-
bility with lower speed products.
TX Signal Dynamic
The dynamic of data signal for both TX DACs is 12 bits extracted from the available signed 16 bit repre-
sentationcoming from the digital processor.
The maximal positive number is 214-1, the most negative number is -214, the 3 LSBs are filled with ’0’.
Any signal exceeding these limits is clamped to the maximum value.
Table 23.
BIT MAP/NIBBLE
TXD0
TXD1
TXD2
TXD3
N0
not used
not used
not used
d0 = data bit 0 (LSB)
N1
data bit 1
data bit 2
data bit 3
data bit 4
N2
data bit 5
data bit 6
data bit 7
data bit 8
N3
data bit 9
data bit 10
data SIGN
data SIGN
Table 24. TX bit map
N3
N2
N1
N0
sign sign d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 n.u. n.u. n.u.
The two sign bits must be identical.
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