STLC60134S View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC60134S' PDF : 22 Pages View PDF
STLC60134S
Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the low going
edge of CLKM/CLKNIB. This holds for the data stream from STLC60134S and from the digital processor.
Data,CLWD setup and hold times are 5ns with reference to thefalling edgeof CLKM/CLKNIB. (not floating).
POWER DOWN
When pin Pdown = ”1”, the chip is set in power down mode. As the Pdown signal is synchronously sam-
pled, minimum duration is 2 periods of the 35MHz clock. In this mode all analog functional blocks are
deactivated except: preamplifiers (TX), clock circuits for output clock CLKM. Pdown will not affect the digi-
tal part of the chip. Anyway, after a Pdown transition, the digital part status, is updated after 3 clock peri-
ods (worst case)
The chip is activated when Pdown = ”0”.
In power down mode the following conditions hold:
- Output voltages at TXP/TXN = AGND
- Preamplifier is on with maximum gain setting (0dB), (digitalgain setting coefficients are overruled)
- The XTAL outputclock on pin CLKM keepsrunning.
- All digital setting are retained.
- Digital output on pins RXDx don’t care (not floating).
In power-down mode the power consumption is 100mW.
Following external conditions are added:
- Clock pin CLW is running.
- CTRLIN signals can still be allowed.
- AGND remains at AVDD/2 (circuit is powered up)
- Input signal at TXDx inputs are not strobed.
The Pdown signal controls asynchronously the power-down of each analog module:
- After a few µs the analog channel is functional
- After about 100ms the analog channel delivers full performance
RESET FUNCTION
The reset function is implied when the RESETN pin is at a low voltage input level. In this condition, the
reset function can be easily used for power up reset conditions.
Detailed Description
During reset: (reset is asynchronous, tenths of ns are enough to put the IC in reset)
All clock outputs are deactivatedand put to logical ”1” (except for the XTAL and master clock CLKM)
After reset: (4 clock periods after reset transition, as worst case)
- OSR = 4
- All analog gains (RX, TX) are set to minimum value
- Nominal filter frequency bands(138kHz, 1.104Hz)
- LNA input = ”11” (max. attenuation)
- VCO dac disabled
- Depending of the LTNT pin value the following configuration is chosen:
’0’ (ATU-R)
RX: LNA -> HC2 -> ADC
TX: DAC -> SC2 -> TX
’1’ (ATU-C)
RX: LNA -> SC2 -> ADC
TX: DAC -> HC2 -> TX
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