STLC60134S View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC60134S' PDF : 22 Pages View PDF
STLC60134S
RX Signal Dynamic
The dynamic of the signal from the ADC is limited to 13bits. Those bits are converted to a signed (2’s
complement) representation with a maximal positive number of 214 -1 and a most negative number -214.
The 2 LSBs are filled with ’0’.
Table 25.
BIT MAP/NIBBLE
RXD0
RXD1
RXD2
RXD3
N0
0
0
d0 = data bit 0 (LSB)
data bit 1
N1
data bit 2
data bit 3
data bit 4
data bit 5
N2
data bit 6
data bit 7
data bit 8
data bit 9
N3
data bit 10
data bit 11
data SIGN
data SIGN
Table 26. RX bit map
N3
N2
N1
N0
sign sign d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0
0
The two sign bits must be identical.
Figure 13. TX/ RX Digital Interface Timing
CLKM
35.328MHz
CLWD
8.832MHz
TXDx/RXDx
CLKNIB
17.664MHz
CLWD
4.416MHz
N0 N1 N2 N3
OSR=4
TXDx/RXDx
N0
N1
N2
N3
D98TL366
OSR=2
Receive / Transmit interface timing
The interface is a triple (RX, TX) nibble - serial interface running at 8.8MHz sampling (normal mode).
The data are represented in 16bits format, and transferred in groups of 4 bits (nibbles). The LSBs are
transferred first. The STLC60134S generates a nibble clock (CLKM master clock in normal mode,
CLKNIB in OSR = 2 mode) and word signals shared by the three interfaces.
Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the falling
edge of CLKM/CLKNIB. This holds for the data stream from STLC60134S and from the digital proces-
sor.
Data, CLWD setup and hold times are 5ns with reference to the falling edge of CLKM/CLKNIB.
(not floating).
17/22
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