STV9410 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV9410' PDF : 25 Pages View PDF
STV9410
Figure 8 : Horizontal Synchronization Timing
DESIGNATION
TIMING DIAGRAM
PIXEL CLOCK
START
Y OUTPUT
0 Start
Margin
Active Area (320 pixels) Margin End of line 0
START
”HORT” MSB REG
”HORT” LSB REG
”HSYN” LSB REG
”HSYN” MSB REG
HSYN PULSE
COMMENTS
Crystal = 8MHz
pxlck = 125ns
0 = origin
DAC output
8pxlck Fixed
= (MG +1) x 8 x pxlck
= (L +1) x 8 x pxlck
= (SD + 1) x 2 x pxlck
= (SU + 1) x 2 x pxlck
Video Validation and Port Register (PORT)
Internal address : 2FF7-2FF6 h
RESET value :00-00 h
(@ = RESET default configuration)
2FF7 VOE - - - - - TE PV
@
00000000
2FF6 N7 N6 N5 N4 N3 N2 N1 N0
@
00000000
VOE
TE
PV
N(7:0)
: Video Output Enable
1 enable synchro & video outputs
0 disable synchro & video outputs @
(@ Output Y, CSYNC, VSYNC, R, G, B, I, POR,
and DF are grounded, Input SYNC IN is high
impedance)
: Timer Enable
1 POR provides a square wave signal with a
period of 16 x N(7:0) x pxlck
0 POR output is PV bit @
: Port Value
POR output value if TE=0 (@=0)
: Square wave period on POR if TE=1 (@=0)
BEWARE
The programmation of VERT, HORI, HSYN regis-
ters must be consistent. To get a proper work of the
controller, the following conditions must, in any
mode (CRT or LCD), be fulfiled :
- SU ≠ SD
-
SU +
4
1
<
L
and
SD +
4
1
<
L
- 2(MG + 1) + 40 ≤ L
Line period is :
- PL = [L(5:0) + 1] x 8 pxlck
- In LCD, MG(2:0) can be 0, then minimum Line
Period is PL (min.) = 43 x 8 pxlck
Frame period is :
- PF = [F(8:0) + 2] x PL
- In LCD, using a 240 lines matrix, F(8:0) = 238,
then minimum frame is :
PF (min.) = 240 x 43 x 8 pxclk
Pixel period is :
-
Pxclk
=
[
F(8:0)
+
PFrame
2 ] [ L(5:0)
+
1
]
x
8
- In LCD, using a 240 lines matrix, and
MG(2:0)
=
0,
Pxclk
=
PFrame
240 x 43 x
8
Interlaced mode conditions :
- SU + 1 and SD + 1 < L
4
4
-
SU +
4
1
and
SD +
4
1
>
(MG
+
1)
+ 42
13/25
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