STV9410 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV9410' PDF : 25 Pages View PDF
STV9410
Figure 12 : ADDR Register and Descriptor List Address
2FF9
2FF8
ADDR REGISTER - P12 P11 P10 P9 P8 P7 P6 - G12 G11 G10 - A12 A11 A10
Used for RAM character sets
REAL ADDRESS
PROG VALUE
010000000000000
2
0
-
-
(0800h)
REAL ADDRESS
PROG VALUE
101011100000000
5
7
-
-
(15C0h)
REAL ADDRESS
PROG VALUE
010100100000000
2
9
-
-
64 bytes blocks
(0A40h)
3.3 DISPLAY REGISTER (DISP)
Internal address : 2FFB-2FFAh
RESET value :00-00 h
(@ = RESET default configuration)
2FFB IMG GMG RMG BMG - - - HIC
@ 0 0 0 0 0000
2FFA FLE CCE IN1 IN0 BR3 BR2 BR1 BR0
@ 0 0 0 0 0000
IMG,
GMG,
RMG,
BMG
: Margin value of I,G,R,B outputs and
background color and insertion default attribute
of next alphanumeric character. In case of
graphic characters only I is default attribute.
HIC : Forces alphanumeric characters background
black (R, G, B = 0), and foreground white (R, G,
B = 1) for maximum contrast, 0 = disable @
FLE : Flashing enable, 0 = disable @
CCE : Conceal enable, 0 = disable @
IN1,IN0 : Insertion attribute mode selection. Mode
selects value of I output during active area of
scan line in CRT mode; I output value (during
margin) is programmed with DISP register;
during uniform strip I output value is set
according to strip descriptor.
During active time slot :
0 0 : I output gets value of current code I
attribute (margin attribute or control
character attribute ) @
0 1 : I is set (”1”)
1 0 : I output gets value of current code I
attribute if I=0 R,G,B are reset to ”0”
0 1 : Reserved mode
BR(3:0) :
This value is combined with pixel value to drive
Y DAC in CRT mode :
Y= 4xG + 2xR + B + BR(2:0) + 3x(R or G or B)
(logical or)
R, G, B, I, Y, = 0 during line flyback.
Black level is output with R, G, B = ”0”.
White level is output with R, G, B = ”1”.
During frame flyback, R, G, B, I, Y provides signal
according to uniform strip descriptor FFB bit state
(see chapter 4.2.1)
During LCD mode BR(3:0) drives continuously Y
DAC. Notice that only bit 0 to 2 of BR are used in
CRT mode.
3.4. CURSOR REGISTER (CURS)
Internal address : 2FFD-2FFC h
RESET value : 00-00 h
(@= RESET default configuration)
2FFD CEN CBL CUL - C12 C11 C10 C9
@ 00000000
2FFC C8 C7 C6 C5 C4 C3 C2 C1
@ 00000000
CEN : Cursor enable, 0 = disable @
CBL : 0 cursor blinking off, character blinking
attribute unchanged @
1 cursor blinking on, blinking is mixed with
character blinking attribute. Blinking frequency
is around 1Hz and duty cycle 50%
CUL : 0 character underline attribut is complemented
on cursor position @
1 character color is complemented on cursor
position
C(12:1) : Cursor address (not a screen position)
17/25
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