STV9410 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV9410' PDF : 25 Pages View PDF
STV9410
2.3.2. CRT Mode
In CRT mode, the Vsync signal appears at the first
two lines of the first strip of the descriptor list. It is
recommended to provide an uniform blanked (with
FFB bit) strip as first descriptor. The scan line
number of this strip have to be equal or higher than
scan line number of the vertical blanking Interval.
Master Mode
This mode is selected by writing VSE and HSE bit
of VERT register with logical value ”0”.
Non-interlaced mode is selected by writing ILC bit
of VERT register with logical value ”0”.
Horizontal or composite synchronization signal is
output on CSYNC pin, Vertical synchronization sig-
nal is output on VSYNC pin.
Signal waveforms are described in Figure 9.
Interlaced mode is selected by writing ILC bit of
VERT register with logical value ”1”.
Even frame is identical to non-interlaced frame.
VSYNC PULSE is low during second half of last line
of previous Odd frame and during the two first lines
of current Even frame.
Odd frame is one scan line more than Even frame.
VSYNC PULSE is low during the two first lines and
up to first half of the third line of current Odd frame.
Half line corresponds to 17th character position.
Signals waveforms are described in Figure 10.
Slave Mode
This mode is activated by writing VSE and/or HSE
bit of VERT register with logical value ”1”. Then
SYNC IN input signal is sampled according to
procedure described below.
Vertical Synchronization
SYNC IN signal may be either a vertical synchroni-
zation or a composite synchronization. It is sam-
pled on first pixel of each scan line active area. As
soon as SYNC IN signal low level is detected,
vertical time base counter F(8:0) of VERT register
is reset without any modification of other time base
registers.
Horizontal Synchronization
SYNC IN is sampled one pxlck before and one
pxlck after internal horizontal pulse transition. If
falling edge is not found, one pixel period is added
to internal line duration. Using a line frequency
locked clock applied on XTI, internal scan line
becomes phase locked after few scan line periods
at programmed value (see Figure 11).
2.3.3 LCD Mode
LCD mode only works as a master mode with 320
pixels per line. Internal algorithm allows 8 grey
levels on passive LCD matrix. Number of scan line
is programmable. In order to get maximum refresh
frequency of display, margin and line duration must
be reduced to miminum. Interlaced mode and ex-
ternal synchronization are not allowed. The 1st line
of the first descriptor in the description list corre-
spond to the first line of the LCD display. Y output
provides a programmable voltage usable to adjust
contrast of LCD display. To reduce supply current
consumption, when Y output is unused, VSSA must
not be connected to ground, and VREF pin works as
a reset pin. Notice that SYNC IN Pin provides
(CKD) data clock signal.
2.4 POR OUTPUT
POR is a standard I/O pin programmable at logical
level ”1” or ”0”. It can also provide a programmable
square wave signal of period
P = 16 x N(7:0) x pxlck (0 ≤ N ≤ 255).
It can drive a capacitive buzzer (see application
diagram at page 22).
RESET value of PORT is ”0”.
Figure 9 : ODD and EVEN Synchronization Pulses in Non-interlaced Mode
DESIGNATION
H SYNC PULSE
TIMING DIAGRAM
CSYNC PULSE
VSYNC PULSE
”VERT” LSB REG
FN - 1
FN
FN + 1*
F0
F1
F2
F3
LINE NUMBER
N
N+1
N +2
1
2
3
4
* Internal logic adds one more line
COMMENTS
Horizontal Synchro
Composite Synchro
Vertical Synchro
Programmed value
of F (8 : 0) is N
Frame number
of lines is N + 2
14/25
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