STW81103 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STW81103' PDF : 53 Pages View PDF
Electrical specifications
STW81103
Table 5.
Symbol
Electrical specifications (continued)
Parameter
Condition
Min. Typ. Max. Unit
External VCO
Frequency range
Input level
Current consumption
VCO internal buffer
0.625
-10
28
5.0
GHz
+6
dBm
mA
PLL miscellaneous
IPLL Current consumption
Input buffer, prescaler, digital
dividers, misc.
12
mA
tlock
Lockup time(5) (7)
25 kHzPLLbandwidth;within
1 ppm of frequency error
150
μs
1. In order to achieve best phase noise performance 1 V peak level is suggested.
2. The frequency step is related to the PFD input frequency as follows:
- Fstep = FPFD for direct output
- Fstep = FPFD/2 for divided by 2 output
- Fstep = FPFD/4 for divided by 4 output
3. See relationship between ICP and REXT in Section 5.7: Charge pump.
4. The level of the spurs may change depending on PFD frequency, charge pump current, selected channel and PLL loop
BW.
5. Guaranteed by design and specification.
6. When setting a specified output frequency, the VCO calibration procedure must be run in order to select the best sub-range
for the VCO covering the desired frequency. Once programmed at the initial temperature T0 inside the operating
temperature range (-40 ° C to +85 ° C), the synthesizer is able to maintain the lock status only if the temperature drift (in
either direction)
If higher ΔT are
is within
required
the
the
limit specified by ΔTLK, provided that the
”VCO calibration auto-restart“ feature
final temperature T1 is still inside
can be enabled, thus allowing to
the nominal range.
re-start the VCO
calibration procedure automatically when the part loose the lock condition (trigger on lock detector signal).
7. Frequency jump from 2250 to 2400 MHz; it includes the time required by the VCO calibration procedure (7 FPFD cycles with
FPFD=400 kHz).
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