STW81103 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STW81103' PDF : 53 Pages View PDF
General description
4
General description
STW81103
Figure 1: Block diagram shows the separate blocks that, when integrated, form an Integer-N
PLL frequency synthesizer.
The STW81103 consists of two internal low-noise VCOs with buffer blocks, a divider by 2, a
divider by 4, a low-noise PFD (phase frequency detector), a precise charge pump, a 10-bit
programmable reference divider, two programmable counters and a programmable dual-
modulus prescaler. The 5-bit A-counter and 12-bit B-counter, in conjunction with the dual-
modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P
+A. The division ratio of both reference and VCO dividers is controlled through the selected
digital interface (I2C bus or SPI).
The digital interface type is selected through the proper hardware connection of pin
DBUS_SEL (0 V for I2C bus, 3.3 V for SPI).
All devices operate with a power supply of 3.3 V, and can be powered down when not in use.
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