STW81103 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STW81103' PDF : 53 Pages View PDF
STW81103
Circuit description
5.5
Phase frequency detector (PFD)
The PFD takes inputs from the reference and the VCO dividers and produces an output
proportional to the phase error. The PFD includes a delay gate that controls the width of the
anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer
function.
Figure 17 is a simplified schematic of the PFD.
Figure 17. PFD diagram
VDD
D FF
Up
Fref
R
Delay
Fref
VDD
R
D FF
Down
ABL
5.6
Lock detect
This signal indicates that the difference between rising edges of both UP and DOWN PFD
signals is found to be shorter than the fixed delay (roughly 5 ns). The Lock Detect signal is
high when the PLL is locked and low when the PLL is unlocked. Lock Detect consumes
current only during PLL transients.
5.7
Charge pump
This block drives two matched current sources, IUP and IDOWN, which are controlled
respectively by UP and DOWN PFD outputs. The nominal value of the output current is
controlled by an external resistor (connected to the REXT input pin) and a 3-bit word that
allows selection among 8 different values.
The minimum value of the output current is: IMIN = 2*VBG/REXT (VBG~1.17 V)
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