STW81103 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STW81103' PDF : 53 Pages View PDF
STW81103
6
I2C bus interface
I2C bus interface
The I2C bus interface is selected by hardware connection of pin #21 (DBUS_SEL) to 0 V.
Data is transmitted from microprocessor to the STW81103 through the 2-wire (SDA and
SCL) I2C bus interface. The STW81103 is always a slave device.
The I2C bus protocol defines any device that sends data on the bus as a transmitter, and
any device that reads the data as a receiver. The device controlling the data transfer is the
master, and the others are slaves. The master always initiates the transfer and provides the
serial clock for synchronization.
The STW81103 I2C bus supports Fast Mode operation (clock frequency up to 1MHz).
6.1
6.1.1
General features
Data validity
Data changes on the SDA line must only occur when the SCL is low. SDA transitions while
the clock is high are used to identify a START or STOP condition.
Figure 20. Data validity
SDA
SCL
Data line
Stable data
Valid
Change
data
allowed
6.1.2
START and STOP conditions
START condition
A START condition is identified by a transition of the data bus SDA from high to low while the
clock signal SCL is stable in the high state. A START condition must precede any data
transfer command.
STOP condition
A STOP condition is identified by a transition of the data bus SDA from low to high while the
clock signal SCL is stable in the high state. A STOP condition terminates communications
between the STW81103 and the bus master.
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