STW81103 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STW81103' PDF : 53 Pages View PDF
STW81103
Circuit description
Table 9. VCO B performances vs. amplitude setting (Freq = 4.7 GHz)
PLL_A[1:0]
Differential
voltage swing (Vp)
Current
consumption (mA)
PN at 1 MHz
(dBc/Hz)
00
1.1
13
-121
01
1.3
15
-122
10
1.9
11
2.1
22
-126
24
-127
5.9
5.9.1
Output stage
The differential output signal of the synthesizer can be selected by software among three
different signal paths (direct, divider by 2 and divider by 4) providing multi-band capability.
The selection of the output stage is done by programming properly the PD[4:0] bits.
The output stage is an open-collector structure which is able to meet different requirements
over the desired output frequency range by proper connections on the PCB. Refer to
Section 8: Application information for more details on PCB connections.
Output buffer control mode
This control mode allows to enable/disable the output stage by a hardware control pin
(EXT_PD, pin#23) while the PLL stays locked at the desired frequency; in such a way a very
fast switching time is achieved.
This feature can be useful in designing a ping-pong architecture saving the cost of an
external RF switch.
The function of pin#23 (EXT_PD) is set with the OUTBUF_CTRL_EN bit as shown in
Table 10.
Table 10. EXT_PD pin function setting
OUTBUF_CTRL_EN Function of the EXT_PD pin
EXT_PD pin settings
EXT_PD = 0 V Î Device ON
0
Device hardware power down
EXT_PD = 3.3 V Î Device OFF
1
Output Buffer control
EXT_PD = 0 V Î Output Stage ON
EXT_PD = 3.3 V Î Output Stage OFF
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