STW81103 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STW81103' PDF : 53 Pages View PDF
I2C bus interface
Figure 21. START and STOP conditions
STW81103
SCL
SDA
6.1.3
START
STOP
Byte format and acknowledge
Every byte put on the SDA line must be 8 bits long, starting with the most significant bit
(MSB), and be followed by an acknowledge bit to indicate a successful data transfer.
The transmitter releases the SDA line after sending 8 bits of data. During the 9th clock
pulse, the receiver pulls the SDA line low to acknowledge the receipt of 8 bits of data.
Figure 22. Byte format and acknowledge
6.1.4
SCL
1
2
3
7
8
9
//
SDA
MSB
START
//
Acknowledgement
from receiver
Device addressing
The master must first initiate with a START condition to communicate with the STW81103,
and then send 8 bits (MSB first) on the SDA line which correspond to the device select
address and the read or write mode.
The first seven MSBs are the device address identifier, which corresponds to the I2C bus
definition. For the STW81103, the address is set at “1100A2A1A0”, 3 bits programmable.
The 8th bit (LSB) is the read or write (RW) operation bit, which is set to 1 in read mode and
to 0 in write mode.
Following a START condition, the STW81103 identifies the device address on the bus and, if
matched, acknowledges the identification on the SDA bus during the 9th clock pulse.
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