SX1781 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SX1781' PDF : 16 Pages View PDF
SX1781
PLL Frequency Synthesizer with integrated VCO
ADVANCED COMMUNICATIONS & SENSING
FINAL
DATASHEET
10. Registers Description
The memory map of the registers is shown below.
Internal Address Register
D7
D6
D5
D4
D3
D2
NDiv[7:0]
RDiv[5:0]
Squelch Cal_
mode
Table 10 Memory Map of Registers
D1
D0
NDiv[9:8]
Outp_config
[1:0]
Address
byte
Register
Name
Default Read
value Write
0x00 RegNDivLsb 0x00 R/W
0x01 RegNDivMsb 0x00 R/W
0x02
RegRDiv 0x00 R/W
0x03 RegGenCtrl 0x00 R/W
10.1. RegNDivLsb Register
This register is a read/write register. It configures the least significant 8-bits of Ndiv, the feedback divider ratio of the PLL.
As writing RegNDivLsb triggers the calibration of the VCO, the user should first update RegNdivMsb, then configure
RegNdivLsb if both need to be updated in a frequency hop. Doing this avoids wrong calibration sequences and extended
lock times.
10.2. RegNDivMsb Register
This register is a read/write register. Bits [1:0] configure the two most significant bits of Ndiv, the feedback divider ratio of
the PLL.
10.3. RegRDiv Register
This register is a read/write register. The five least significant bits configure the division factor of the Rdiv prescaler of the
PLL.
10.4. RegGenCtrl Register
This register is a read/write register to configure the output and calibration modes.
Register Bits
b[3]
b[2]
b[1:0]
Description
RF out upon Lock Detection:
0 : The RF output is enabled only when the PLL is locked (Default)
1 : The RF output is enabled whatever the Lock detector state.
Calibration mode
0 : Writing to RegNDivLsb triggers calibration (Default)
1 : Writing to RegRDiv or RegNDivLsb triggers calibration
Output Buffer Current
00 : Output current is 3.5 mA (Default)
01 : Output current is 5 mA
10 : Output current is 7.5 mA
11 : Output current is 11 mA
Rev 1 - November 2008
©2008 Semtech Corp.
Page 10
www.semtech.com
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