SX1781 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SX1781' PDF : 16 Pages View PDF
SX1781
PLL Frequency Synthesizer with integrated VCO
ADVANCED COMMUNICATIONS & SENSING
FINAL
DATASHEET
5. RF Characteristics
Table 7 RF Characteristics
Parameter
CLK Input Reference Frequency
PFD Update Frequency (1)
VCO Center Frequency Range
PLL Output Frequency Range
Phase Noise
at 10 kHz offset
Integrated Jitter
Loop Bandwidth
Harmonic Suppression
Maximum RFOUT Power Level
Output Power Tolerance
Output Reference Spurs
Output Spurs
Hopping Time (3)
across entire tuning range
Power Up Request from
SLEEPB rising (3)
(input reference settled)
Power Down Request to
Synthesizer off Time
Symbol
FREF
fφ
FCEN
FOUT
-
-
-
H2
Pout
∆Pout
-
-
thop
tpup
tpdn
Test Conditions
Minimum
External Reference
0.5
fφ= FREF/(Rdiv+1)
500
(2)
-
2400
-
1200
Fout=1290 MHz
-
fφ = 500 kHz
FREF=26 MHz
100Hz to 100kHz
-
Closed Loop
-
Second Harmonic
-
Single output into 50 ohm
-
Differential outputs
-
combined in a balun
-
-3
Offset = 500 kHz
-
All other spurs
-
To +/- 1 ppm precision
-
To LD pin rising edge
-
To +/- 1 ppm precision
-
To LD pin rising edge
-
SLEEPB falling
-
Typical
-
-
-
-
-85
2.4
50
-26
-1
+5
-
-67
-67
-
-
-
-
-
Maximum
26
-
2800
1400
-75
4
-
-20
-
-
+3
-
-
500
350
750
625
100
Units
MHz
kHz
MHz
MHz
dBc/Hz
ps
kHz
dBc
dBm
dBm
dB
dBc
dBc
µs
µs
µs
µs
ns
Notes:
1: Value of Rdiv is as programmed into the input divider
2: PFD update frequency should be maintained as close to 500 kHz as possible for optimum phase noise performance. Other divider values can be
programmed to reduce the PFD update rate, but this is not recommended due to the internal loop bandwidth being preset @ 50kHz.
3: No SPI access should be performed during tpup or thop, while the VCO is being calibrated.
Rev 1 - November 2008
©2008 Semtech Corp.
Page 6
www.semtech.com
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