XE8801A – SX8801R
6.1 Features
• Power On Reset (POR)
• External reset from the RESET pin
• Programmable Watchdog timer reset
• Programmable BusError reset
• Sleep mode management
• Programmable Port A input combination reset
6.2 Overview
The reset block is the reset manager. It handles the different reset sources and distributes them through the
system. It also controls the sleep mode of the circuit.
6.3 Register map
Pos. RegSysCtrl
7 SleepEn
Rw Reset
r w 0 resetcold
6 EnResPConf
r w 0 resetcold
5 EnBusError
4 EnResWD
r w 0 resetcold
r w 0 resetcold
3–0 -
r
0000
Table 6-1. RegSysCtrl register.
Function
enables Sleep mode
0: sleep mode is disabled
1: sleep mode is enabled
enables the resetpconf signal when the
resetglobal is active
0: resetpconf is disabled
1: resetpconf is enabled
enables reset from BusError
0: BusError reset source is disabled
1: BusError reset source is enabled
enables reset from Watchdog
0: Watchdog reset source is disabled
1: Watchdog reset source is enabled
this bit can not be set to 0 by SW
unused
Pos. RegSysReset Rw Reset
7 Sleep
rw 0 resetsystem
6-
r
0
5 ResetBusError r c 0 resetcold
4 ResetWD
r c 0 resetcold
3 ResetfromportA r c 0 resetcold
2 ResPad
r c 0 resetcold
1 ResPadSleep r c 0 resetcold
0-
r
0
Table 6-2. RegSysReset register
Function
Sleep mode control (reads always 0)
unused
reset source was BusError
reset source was Watchdog
reset source was Port A combination
reset source was reset pad
reset source was reset pad in sleep mode
unused
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6-2