SX8801IRXXMLTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SX8801IRXXMLTRT' PDF : 135 Pages View PDF
XE8801A – SX8801R
Symbol
TPOR
Parameter
POR reset duration
TRESET
RESET pin reset duration
TRESET
RESET pin reset duration
Vbat_sl_M Supply ramp up of MTP version
Min Typ Max
5
20
20
200
5
20
20
Unit
ms
µs
ms
V/ms
Comments
3
4
1
Vbat_sl_R Supply ramp up of ROM version 0.25
WDtime Watchdog timeout period
2
Table 6-5. Electrical and timing specifications
V/ms
1
s
2
Note: 1) The Vbat_sl defines the minimum slope required on VBAT. Correct start-up of the circuit is not guaranteed
if this slope is too slow. In such a case, a delay has to be built using the RESET pin.
Note: 2) The minimal watchdog timeout period is guaranteed when the internal oscillators are used. The watchdog
takes its clock from the low prescaler. In case an external clock source is used, the RC oscillator must be enabled
also (EnRC=1 in RegSysClock). Otherwise, the watchdog is stopped (see the clock block documentation).
Note: 3) For the circuit versions XE88LC01 and XE88LC05. Gives the time the reset is active after the falling edge
of the RESET pin.
Note: 4) For the circuit versions XE88LC01A and XE88LC05A. Gives the time the reset is active after the falling
edge of the RESET pin.
© Semtech 2005
www.semtech.com
6-6
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