SX8801IRXXMLTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SX8801IRXXMLTRT' PDF : 135 Pages View PDF
XE8801A – SX8801R
7.8 Prescalers
The clock generator block embeds two divider chains: the high prescaler and the low prescaler.
The high prescaler is made of an 8 stage dividing chain and the low prescaler of a 15 stage dividing chain.
Features:
• High prescaler can only be driven with RC clock (bit EnableRc have to be set, see Table 7-12).
• Low prescaler can be driven from the high prescaler or directly with the Xtal clock when bit EnableXtal is set to
1, bit EnExtClock is set to 0 and ExtClk is equal at 0.
• Bit ResPre in the RegSysPre0 register allows to reset synchronously the low prescaler, the low prescaler is
also automatically cleared when bit EnableXtal is set. Both dividing chains are reset asynchronously by the
resetsleep signal.
• Bit ColdXtal=1 indicates the Xtal is in its start up phase. It is active for 37268 Xtal cycles after setting
EnableXtal.
7.9 32 kHz frequency selector
A decoder is used to select from the high prescaler the frequency tap that is the closest to 32 kHz to operate the
low prescaler when the Xtal is not running. In this case, the RC oscillator frequency of ±50% will also be valid for
the low prescaler frequency outputs.
© Semtech 2005
www.semtech.com
7-9
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