SX8801IRXXMLTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SX8801IRXXMLTRT' PDF : 135 Pages View PDF
XE8801A – SX8801R
16.4.2 Peripheral Registers
Figure 16-2 shows a detailed functional diagram of the ZoomingADC™. In
Table 16-10 the configuration of the peripheral registers is detailed. The system has a bank of eight 8-bit registers:
six registers are used to configure the acquisition chain (RegAcCfg0 to 5), and two registers are used to store the
output code of the analog-to-digital conversion (RegAcOutMsb & Lsb). The register coding of the ADC parameters
and performance characteristics are detailed in Section 16.7.
Table 16-10. Peripheral registers to configure the acquisition chain (AC)
and to store the analog-to-digital conversion (ADC) result
Register
Name
RegAcOutLsb
RegAcOutMsb
RegAcCfg0
Default
values:
RegAcCfg1
Default
values:
RegAcCfg2
Default
values:
RegAcCfg3
Default
values:
RegAcCfg4
Default
values:
RegAcCfg5
Default
values:
Bit Position
7
6
5
4
3
2
1
OUT[7:0]
OUT[15:8]
STAR
T
0
SET_NELC[1:0]
01
SET_OSR[2:0]
010
CONT
0
IB_AMP_ADC[
1:0]
11
IB_AMP_PGA[1:
0]
11
ENABLE[3:0]
0001
0
TEST
0
FIN[1:0]
00
PGA2_GAIN[1:0]
00
PGA2_OFFSET[3:0]
0000
PGA1
_G
0
PGA3_GAIN[6:0]
0000000
PGA3_OFFSET[6:0]
0
0000000
BUSY DEF
0
0
AMUX[4:0]
00000
VMUX
0
With:
• OUT: (r) digital output code of the analog-to-digital converter. (MSB = OUT[15])
• START: (w) setting this bit triggers a single conversion (after the current one is finished). This bit always reads
back 0.
• SET_NELC: (rw) sets the number of elementary conversions to 2SET_NELC[1:0] . To compensate for offsets, the
input signal is chopped between elementary conversions (1,2,4,8).
• SET_OSR: (rw) sets the over-sampling rate (OSR) of an elementary conversion to 2(3+SET_OSR[2:0]) . OSR = 8, 16,
32, ..., 512, 1024.
• CONT: (rw) setting this bit starts a conversion. A new conversion will automatically begin as long as the bit
remains at 1.
• TEST: bit only used for test purposes. In normal mode, this bit is forced to 0 and cannot be overwritten.
• IB_AMP_ADC: (rw) sets the bias current in the ADC to 0.25*(1+ IB_AMP_ADC[1:0]) of the normal operation
current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation.
• IB_AMP_PGA: (rw) sets the bias current in the PGAs to 0.25*(1+IB_AMP_PGA[1:0]) of the normal operation
current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation.
• ENABLE: (rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i=1,2,3). PGA stages that
are disabled are bypassed.
• FIN: (rw) These bits set the sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency,
the sampling frequency is given as: 00 Æ 1/4 fRC, 01 Æ 1/8 fRC, 10 Æ 1/32 fRC, 11Æ ~8kHz.
© Semtech 2005
16-6
www.semtech.com
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