SX8801IRXXMLTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SX8801IRXXMLTRT' PDF : 135 Pages View PDF
XE8801A – SX8801R
16.6.3 PGA2
The second PGA has a finer gain and offset tuning capability, as shown in Table 16-15 and Table 16-16. The voltage
VD2 at the output of PGA2 is given by:
VD2 = GD2 ⋅VD1 − GDoff 2 ⋅VREF (V)
(Eq. 6)
where GD2 and GDoff2 are respectively the gain and offset of PGA2 (in V/V). These are controlled with the words
PGA2_GAIN[1:0] and PGA2_OFFSET[3:0].
As shown in equation 6, the offset correction is directly proportional to the reference voltage. All drifts and
perturbations on the reference voltage will affect the precision of the offset compensation.
16.6.4 PGA3
The finest gain and offset tuning is performed with the third and last PGA stage, according to the coding of Table
16-17 and Table 16-18. The output of PGA3 is also the input of the ADC. Thus, similarly to PGA2, we find that the
voltage entering the ADC is given by:
VIN ,ADC = GD3 ⋅VD2 − GDoff 3 ⋅VREF
(V)
(Eq. 7)
where GD3 and GDoff3 are respectively the gain and offset of PGA3 (in V/V). The control words are
PGA3_GAIN[6:0] and PGA3_OFFSET[6:0] . To remain within the signal compliance of the PGA stages, the
condition:
VD1 ,VD2 < VDD (V)
(Eq. 8)
must be verified.
As shown in equation 7, the offset correction is directly proportional to the reference voltage. All drifts and
perturbations on the reference voltage will affect the precision of the offset compensation.
Finally, combining equations Eq. 5 to Eq. 7 for the three PGA stages, the input voltage VIN,ADC of the ADC is related
to VIN by:
VIN , ADC = GDTOT ⋅VIN − GDoffTOT ⋅VREF (V)
(Eq. 9)
where the total PGA gain is defined as:
GDTOT = GD3 ⋅ GD2 ⋅ GD1
(V/V)
(Eq. 10)
and the total PGA offset is:
GDoffTOT = GDoff3 + GD3 ⋅ GDoff2
(V/V)
(Eq. 11)
© Semtech 2005
16-11
www.semtech.com
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