T89C51AC2-SLSIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'T89C51AC2-SLSIM' PDF : 121 Pages View PDF
External Code Memory Access
Memory Interface
The external memory interface comprises the external bus (port 0 and port 2) as well as
the bus control signals (PSEN#, and ALE).
Figure 18 shows the structure of the external address bus. P0 carries address A7:0
while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 18
describes the external memory interface signals.
Figure 18. External Code Memory Interface Structure
A/T89C51AC2
P2
ALE
P0
A15:8
AD7:0 Latch A7:0
PSEN#
Flash
EPROM
A15:8
A7:0
D7:0
OE
Table 22. External Code Memory Interface Signals
Signal
Name Type Description
A15:8
O
Address Lines
Upper address lines for the external bus.
AD7:0
I/O
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
Address Latch Enable
ALE
O ALE signals indicates that valid address information are available on lines
AD7:0.
PSEN#
Program Store Enable Output
O This signal is active low during external code fetch or external code read
(MOVC instruction).
Alternate
Function
P2.7:0
P0.7:0
-
-
External Bus Cycles
This section describes the bus cycles the A/T89C51AC2 executes to fetch code (see
Figure 19) in the external program/code memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-
mation on X2 mode see section “Clock “.
For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized
form and do not provide precise timing information.
For bus cycling parameters refer to the ‘AC-DC parameters’ section.
34 A/T89C51AC2
4127H–8051–02/08
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