TCS3404 View Datasheet(PDF) - austriamicrosystems AG
Part Name
Description
MFG CO.
'TCS3404' PDF : 56 Pages View PDF
Figure 35:
Command Register
7
CMD
6
5
TRANSACTION
TCS3404, TCS3414 − Principles of Operation
Command Register
The Command Register specifies the address of the target
register for subsequent read and write operations. This register
contains eight bits as described in Figure 35 and defaults to 00h
at power on.
4
3
2
1
0
ADDRESS
Field
CMD
TRANSACTION
ADDRESS
Bits
7
6:5
4:0
Description
Select Command Register. Must write as 1.
Transaction. Selects type of transaction to follow in subsequent data transfer.
Field Value
Transaction
Description
00
Byte protocol SMB read/write byte protocol
01
Word protocol SMB read/write word protocol
10
Block protocol SMB read/write block protocol
11
Interrupt clear
Clear any pending interrupt and is a
write-once-to-clear field
Register Address. This field selects the specific control or status register for
following write and read commands according to Figure 34.
Note(s):
1. An I2C block transaction will continue until the Master sends a stop condition. See Figure 30 and Figure 31. Unlike the I2C protocol,
the TCS3404/14 SMBus read/write protocol requires a Byte Count. All eight ADC Channel Data Registers (10h through 17h) can be
read simultaneously in a single SMBus transaction. This is the only 64-bit data block supported by the TCS3404 SMBus protocol. The
TRANSACTION field must be set to 10, and a read condition should be initiated with a COMMAND CODE of CFh. By using a COMMAND
CODE of CFh during an SMBus Block Read Protocol, the TCS3404 device will automatically insert the appropriate Byte Count (Byte
Count = 8) as illustrated in Figure 30. A write condition should not be used in conjunction with the 0Fh register.
2. Only the Send Byte Protocol should be used when clearing interrupts.
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[v1-00] 2015-Nov-11
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