TCS3404 View Datasheet(PDF) - austriamicrosystems AG
Part Name
Description
MFG CO.
'TCS3404' PDF : 56 Pages View PDF
TCS3404, TCS3414 − Principles of Operation
Figure 36:
Control Register
Control Register (00h)
The Control Register contains two bits and is primarily used to
power the TCS3404/14 device up and down as shown in
Figure 36.
7
Resv
6
Resv
5
Resv
4
ADC_VALID
3
Resv
2
Resv
1
ADC_EN
0
POWER
Field
Resv
ADC_VALID
Resv
ADC_EN
POWER
Bits
7:5
4
3:2
1
0
Description
Reserved. Write as 0.
ADC valid. This read-only field indicates that the ADC channel has completed an
integration cycle.
Reserved. Write as 0.
ADC enable. This field enables the four ADC channels to begin integration. Writing
a 1 activates the ADC channels, and writing a 0 disables the ADCs.
Power On. Writing a 1 powers on the device, and writing a 0 turns it OFF.
Note(s):
1. Both ADC_EN and POWER must be asserted before the ADC channels will operate correctly.
2. INTEG_MODE and TIME/COUNTER fields in the Timing Register (01h) should be written before ADC_EN is asserted.
3. If a value of 03h is written, the value returned during a read cycle will be 03h. This feature can be used to verify that the device is
communicating properly.
4. During writes and reads, the POWER bit is overridden and the oscillator is enabled, independent of the state of POWER.
ams Datasheet
[v1-00] 2015-Nov-11
Page 23
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