TDA7505
Electrical specifications
Table 19. Debug port interface (continued)
No.
Characteristics (Fdsp = 75MHz)
8 DBCK high to DBOUT invalid
9 DBIN valid to DBCK low (set-up)
10 DBCK low to DBIN invalid (hold)
DBOUT (ACK) asserted to first DBCK high
DBOUT (ACK) assertion width
11
Last DBCK low of read register to first DBCK
high of next command
12 Last DBCK low to DBOUT invalid (hold)
DBSEL setup to DBCK
Figure 9. Debug port serial clock timing
DBCK
(input)
(1)
(3)
(5)
Min.
3
15
3
2*TDSP
5*TDSP - 3
7*TDSP + 10
3
TDSP
Max.
Unit
ns
ns
ns
ns
5*TDSP + 7
ns
ns
ns
ns
(2)
(4)
D02AU1363
Figure 10. Debug port acknowledge timing
DBRQN
(input)
DBOUT
(output)
(6)
D02AU1364
(ACK)
Figure 11. Debug port data I/O to status timing
DBCK
(input)
DBOUT
(output)
DBIN
(input)
(9)
(10)
Note:
1 High Impedance, external pull-down resistor
(Last)
(Note 1)
D02AU1365
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