TDA7505 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7505' PDF : 38 Pages View PDF
TDA7505
Functional description
5.2.2
5.2.3
5.2.4
Program RAM
This is a 24-Bit Single Port SRAM used for storing and executing program code. The 16-Bit
PRAM Address, PABx(15:0) is generated by the Program Address Generator of the DSP
core for Instruction Fetching, and by the AGU in the case of the Move Program Memory
(MOVEM) Instruction. The 24-Bit PRAM Data (Program Code), PDBx(23:0), can only be
written to using the MOVEM instruction. During instruction fetching the PDBx Bus is routed
to the Program Decode Controller of the DSP core for instruction decoding.
Program ROM
This is a 24-Bit Single Port mask programmable ROM used for storing and executing
program code. Additionally the boot loader SW is placed here. Essentially this consists of
reading the data via I2C, SPI or EMI interface and store it in PRAM, XRAM and YRAM. The
16-Bit PROM Address, PABx(15:0) is generated by the Program Address Generator of the
DSP core for Instruction Fetching, and by the AGU in the case of the Move Program
Memory (MOVEM) Instruction. The 24-Bit PROM Data (Program Code), PDBx(23:0), can
only be read but not written. During instruction fetching the PDBx Bus is routed to the
Program Decode Controller of the DSP core for instruction decoding.
Serial audio interface (SAI)
The SAI is used to deliver digital audio to the device from an external source. Once
processed by the device, either it can be returned through this interface or sent to the DAC
for D/A conversion. The features of the SAI are listed below:
● 3 Synchronized Stereo Data Transmission Lines
● 3 Synchronized Stereo Data Reception Lines
● Master and Slave operating mode: clock lines can be both master and slave.
● Receive and Transmit Data Registers have two locations to hold left and right data.
Serial peripheral interface (SPI)
The DSP core requires a serial interface to receive commands and data over the LAN.
During an SPI transfer, data are transmitted and received simultaneously. A serial clock line
synchronizes shifting and sampling of the information on the two serial data lines. A slave
select line allows individual selection of a slave SPI device.
When an SPI transfer occurs an 8-bit word is shifted out through one data pin while another
8-bit word is simultaneously shifted in through a second data pin. The central elements in
the SPI system are the shift register and the read data buffer. The system is single buffered
in the transfer direction and has a 10 word buffer in the receive direction (only master SPI;
the display SPI is single word buffered only).
Sony/Phillips digital interface (S/PDIF)
The S/PDIF receiver is a serial digital audio interface. It receives and decodes serial audio
data according to one of the following standards: AES/EBU, IEC 958, S/PDIF, and EIAJ CP-
340 in a frequency range from 32kHz up to 96kHz. The transfer protocol provides two audio
data channels.
There is a direct output connected to Asynchronous Sample Rate Converter. Left and right
20 bit audio-channels and sample clock are provided.
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