Functional description
TDA7505
5.2
5.2.1
DSP peripherals
There are a number of peripherals that are tightly coupled to the two DSP Cores. Some of
the peripherals are connected to DSP 0 others are connected to DSP 1.
● 4k x 24-Bit Program RAM for DSP0
● 16k x 24-Bit mask programmable Program ROM for DSP0
● 4k x 24-Bit X-Data RAM for DSP0
● 4k x 24-Bit Y-Data RAM for DSP0
● 4k x 24-Bit Program RAM for DSP1
● 16k x 24-Bit mask programmable Program ROM for DSP1
● 4k x 24-Bit X-Data RAM for DSP1
● 4k x 24-Bit mask programmable X-Data ROM for DSP1
● 4k x 24-Bit Y-Data RAM for DSP1
● 6 channel Serial Audio Interface (SAI)
● 2 channel SPDIF receiver with sampling rate conversion
● I2C and SPI interfaces
● XCHG Interface for DSP to DSP communication
● External Memory Interface (DRAM/SRAM) for time-delay and traffic information
● Debug Port for both DSP´s
● General-purpose Input/Output lines
● Asynchronous Sample Rate Converter
● SINCOS co-processor
● PLL Clock Oscillator
● ADC´s, ADC input multiplexer and DAC´s (see Section 5.2.12: CODEC on page 32)
Data and program memories
Both DSP0 and DSP1 have data and program memories attached to them. Each memory
type is described below:
X-RAM
This is a 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit XRAM address,
XABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit XRAM
Data, XDBx(23:0), may be written to and read from the Data ALU of the DSP core.
X-ROM
This is a 24-Bit Single Port mask programmable ROM used for storing coefficients. The 16-
Bit XRAM address, XABx(15:0) is generated by the Address Generation Unit of the DSP
core. The 24-Bit XRAM Data, XDBx(23:0), may be read from the Data ALU of the DSP core.
Y-RAM
This is a 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit address,
YABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit Data,
YDBx(23:0), is written to and read from the Data ALU of the DSP core.
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