TDA75612LV
9
I2C bus
I2C bus
9.1
I2C programming/reading sequences
A correct turn on/off sequence with respect to the diagnostic timings and producing no
audible noises could be as follows (after battery connection):
Turn-on: PIN2 > 4.5 V - wait for 10 ms - (STAND-BY OUT + DIAG ENABLE) - wait for
1s - Muting out (play with no signal) - wait for 100ms
Turn-off: MUTING IN - wait for 50 ms - HW ST-BY IN (ST-BY pin ≤ 1.2 V)
Car Radio Installation: PIN2 > 4.5 V - wait for 10 ms - DIAG ENABLE (write) - wait for
200 ms - I2C read (repeat until all faults disappear).
9.2
Address selection and I2C disable
When the ADSEL/I2CDIS pin is left open the I2C bus is disabled and the device can be
controlled by the STBY/MUTE pin.
In this status (no - I2C bus) the DATA pin sets the gain (0 = 30 dB; 1 = 16 dB).
When the ADSEL/I2CDIS pin is connected to GND the I2C bus is active with address
<1101100-x>.
To select the other I2C address a resistor must be connected to ADSEL/I2CDIS pin as
following:
0 < R < 1 kΩ: I2C bus active with address <1101100x>
11 kΩ < R < 21 kΩ: I2C bus active with address <1101101x>
40 kΩ < R < 70 kΩ: I2C bus active with address <1101110x>
R > 120 kΩ: Legacy mode
(x: read/write bit sector)
9.3
9.3.1
9.3.2
I2C bus interface
Data transmission from microprocessor to the TDA75612LV and viceversa takes place
through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up
resistors to positive supply voltage must be connected).
Data validity
As shown by Figure 21, the data on the SDA line must be stable during the high period of
the clock. The HIGH and LOW state of the data line can only change when the clock signal
on the SCL line is LOW.
Start and stop conditions
As shown by Figure 22 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.
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