Product Datasheet
Jan 4, 2012
TGA4953-SL
Typical Bias Conditions
Vdd=5V
Vo(V) Vg1(V) Vg2(V)
Idd
6
-0.66
-0.57
221
5
-0.66
-0.59
198
4
-0.66
-0.67
172
3
-0.66
-0.74
147
Notes:
1. Vdd=5V, Id1=65mA, and Vctrl1=-0.2V
2. Vin=500mVpp
3. 50%CPC
4. Actual bias points may be different.
Vctrl2
+0.22
+0.04
-0.14
-0.34
General Comments for Production Operation of TGA4953-SL:
1.
Due to natural variations in gate voltages observed with GaAs FET amplifiers used internally to
the TGA4953-SL, optimal eye performance is obtained when the gate voltages (Vg1 and Vg2)
are set to control desired drain currents (Id1 and Id2T)
2.
Vc2 feedback circuit recommended for output amplitude correction.
TriQuint Semiconductor: www. triquint.com (972)994-8465 Fax (972)994-8504 info-networks@tqs.com 12