Application Information
TS4972
Figure 82: Flip-Chip 300µm Demoboard Top
Solder Layer
Figure 83: Flip-Chip 300µm Demoboard
Bottom Solder Layer
■ BTL Configuration Principle
The TS4972 is a monolithic power amplifier with a
BTL output type. BTL (Bridge Tied Load)
means that each end of the load is connected
to two single ended output amplifiers. Thus, we
have :
Single ended output 1 = Vout1 = Vout (V)
Single ended output 2 = Vout2 = -Vout (V)
And Vout1 - Vout2 = 2Vout (V)
The output power is:
Pout = (2 Vout RMS )2 (W)
RL
For the same power supply voltage, the output
power in BTL configuration is four times higher
than the output power in single ended
configuration.
■ Gain In Typical Application Schematic
(cf. page 1)
In flat region (no effect of Cin), the output voltage
of the first stage is:
Vout1 = –Vin R-----f-R--e---ie-n---d---- (V)
For the second stage : Vout2 = -Vout1 (V)
The differential output voltage is:
Vout2 – Vout1 = 2Vin R-----f-R--e--i-e-n---d---- (V)
The differential gain named gain (Gv) for more
convenient usage is:
Gv = V-----o---u---t--2--V---–--i--nV-----o----u---t---1- = 2 R-----f-R--e--i-e-n---d----
Remark : Vout2 is in phase with Vin and Vout1 is
180 phased with Vin. It means that the positive
terminal of the loudspeaker should be
connected to Vout2 and the negative to Vout1.
■ Low and high frequency response
In low frequency region, the effect of Cin starts.
Cin with Rin forms a high pass filter with a -3dB
cut off frequency.
FCL = --2----π------R---1--i--n-----C-----i-n- (Hz)
In high frequency region, you can limit the
bandwidth by adding a capacitor (Cfeed) in
parallel on Rfeed. Its form a low pass filter with
a -3dB cut off frequency.
FCH = --2----π------R-----f--e----e1----d-----C----f--e---e----d- (Hz )
■ Power dissipation and efficiency
Hypothesis :
• Voltage and current in the load are
sinusoidal (Vout and Iout)
• Supply voltage is a pure DC source (Vcc)
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