UPD703017AGC View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
MFG CO.
'UPD703017AGC' PDF : 48 Pages View PDF
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Clock Timing
(1) Operating conditions (TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load
capacitance: CL = 50 pF)
Parameter
X1 input cycle
XT1 input cycle
X1 input high-level width
XT1 input high-level width
X1 input low-level width
XT1 input low-level width
X1 input rise time
Symbol
tCYX
<1>
tWXH
<2>
tWXL
<3>
tXR
<4>
Conditions
X1 input fall time
tXF
<5>
CLKOUT output cycle
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
CLKOUT fall time
tCYK
tWKH
tWKL
tKR
tKF
<6>
<7>
<8>
<9>
<10>
Remarks 1. T = tCYK
2. Ensure that the duty is between 45% and 55%.
MIN.
MAX.
Unit
58.8
ns
28.5
µs
26.4
ns
12.8
µs
26.4
ns
12.8
µs
0.5 (tCYX –
ns
tWXH – tWXL)
0.5 (tCYX –
ns
tWXH – tWXL)
58.8 ns
31.2 µs
0.4tCYK – 10
ns
0.4tCYK – 10
ns
10
ns
10
ns
(2) Operating conditions (TA = –40 to +85°C, VDD = BVDD = 3.0 to 3.6 V, VSS = BVSS = 0 V, Output pin load
capacitance: CL = 50 pF)
Parameter
X1 input cycle
XT1 input cycle
X1 input high-level width
XT1 input high-level width
X1 input low-level width
XT1 input low-level width
X1 input rise time
Symbol
tCYX
<1>
tWXH
<2>
tWXL
<3>
tXR
<4>
Conditions
X1 input fall time
tXF
<5>
CLKOUT output cycle
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
CLKOUT fall time
tCYK
tWKH
tWKL
tKR
tKF
<6>
<7>
<8>
<9>
<10>
Remarks 1. T = tCYK
2. Ensure that the duty is between 45% and 55%.
MIN.
MAX.
Unit
50.0
ns
28.5
µs
22.5
ns
12.8
µs
22.5
ns
12.8
µs
0.5 (tCYX –
ns
tWXH – tWXL)
0.5 (tCYX –
ns
tWXH – tWXL)
50.0 ns
31.2 µs
0.4tCYK – 10
ns
0.4tCYK – 10
ns
10
ns
10
ns
Data Sheet U14526EJ2V0DS00
29
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