UPD78P058F View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
MFG CO.
'UPD78P058F' PDF : 415 Pages View PDF
CHAPTER 1 GENERAL
Table 1-13. Functional Outline of µPD780308 Subseries
Part Number
Item
µPD780306
µPD780308
µPD78P0308
Internal ROM
memory
Mask ROM
48K bytes
60K bytes
PROM
60K bytesNote
High-speed RAM 1024 bytes
Expansion RAM 1024 bytes
LCD display RAM 40 × 4 bits
Memory space
64K bytes
General-purpose register 8 bits × 8 × 4 banks
Minimum With main
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0 MHz)
instruction system clock
execution With subsystem 122 µs (at 32.768 kHz)
time
clock
Instruction set
• 16-bit operation
• Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjustment, etc.
I/O port
• Total
: 57
(including pins multiplexed • CMOS input : 2
with segment signal output) • CMOS I/O : 55
A/D converter
8-bit resolution × 8 channels
LCD controller/driver
• Segment signal output : 40 max.
• Common signal output : 4 max.
• Bias
: 1/2 or 1/3 bias selectable
Serial interface
• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable
• 3-wire serial I/O/UART mode selectable
• 3-wire serial I/O mode
: 1 channel
: 1 channel
: 1 channel
Timer
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer
: 1 channel
• Watchdog timer
: 1 channel
Timer output
3 (14-bit PWM output: 1)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with
main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)
Vectored Maskable
Internal: 13, external: 6
interrupt Non-maskable Internal: 1
Software
1
Test input
Internal: 1, external: 1
Supply voltage
VDD = 2.0 to 5.5 V
Package
• 100-pin plastic QFP (fine pitch) (14 × 14 mm)
• 100-pin plastic QFP (14 × 20 mm)
• 100-pin ceramic WQFN (14 × 20 mm) (µPD78P0308 only)
Note The capacity of the internal PROM can be changed by using a memory size select register (IMS).
Caution The µPD780308 subseries is under development.
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