V961PBC-40REVB2 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'V961PBC-40REVB2' PDF : 16 Pages View PDF
V961PBC
Table 13: Local Bus Timing Parameters for Vcc = 5 Volts +/- 5%
33MHz
40MHz
# Symbol
Description
Notes Min Max Min Max Units
1 TC LCLK period
30
25
ns
2 TCH LCLK high time
1
12
11
ns
3 TCL LCLK low time
1
12
11
ns
4 TSU Synchronous input setup
2
7
6
ns
4a TSU Synchronous input setup (BLAST)
8
7
ns
4b TSU Synchronous input setup (W/R, BTERM)
4
4
ns
4c TSU Synchronous input setup (ADS)
6
5
ns
4d
TSU
Synchronous input setup (address, data,
byte enables)
9
8
ns
4e
TSU
Synchronous input setup for read data
when in local bus master mode
5
5
ns
5 TH Synchronous input hold
6 TCOV LCLK to output valid delay
3
6a
TCOV
LCLK to output valid delay (address, data,
byte enable, parity)
2
2 ns
3 14 3 12 ns
3 15 3 14 ns
7 TCZO LCLK to output driving delay
8 TCOZ LCLK to high impedance delay
9 TRST Reset period when LRST used as input
3 15 3 14 ns
4
3 15 3 14 ns
16·TC
16·TC
ns
Notes:
1. Measured at 1.5V.
2. All local bus signals except those in 4a, 4b, 4c, 4d and 4e.
3. All local bus signals except those in 6a.
4. RDYRCV, BLAST, ADS are driven to high impedance at the falling edge of LCLK.
Table 14: ALE Timing Parameters for Vcc = 5 Volts +/- 5%
# Symbol
Description
1 TALE ALE Pulse Width
2
TASUO
Address setup to ALE falling
(ALE as output)
33MHz
40MHz
Min Max Min Max Units
TCH-4
TCH-4
ns
TCH-5
TCH-4
ns
Copyright © 1998, V3 Semiconductor Inc.
V961PBC Data Sheet Rev 2.4
13
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