V961PBC-40REVB2 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'V961PBC-40REVB2' PDF : 16 Pages View PDF
V961PBC
Table 14: ALE Timing Parameters for Vcc = 5 Volts +/- 5%
3
TAHO
Address hold from ALE falling
(ALE as output)
TCL-5
TCL-4
ns
4 TASUI
Address setup to ALE falling
(ALE as input)
5
5
ns
5
TAHI
Address hold from ALE falling
(ALE as input)
5
5
ns
Table 15: PCI Bus Timing Parameters for Vcc = 5 Volts +/- 5%
# Symbol
Description
1
TC PCLK period
2
TSU Synchronous input setup to PCLK
2a TSU Synchronous input setup to PCLK (GNT)
3
TH Synchronous input hold from PCLK
4 TCOV PCLK to output valid delay
4a TCOV PCLK to output valid delay (REQ)
5 TCZO PCLK to output driving delay
6 TCOZ PCLK to high impedance delay
7 TRST Reset period when PRST used as input
Notes Min Max Units
30
ns
1
7
ns
10
ns
0
ns
2
3
11 ns
4
12 ns
4
11 ns
5
18 ns
16·TC
Notes:
1. All PCI bus signals except those in 2a.
2. All PCI bus signals except those in 4a.
4.3 Serial EEPROM Port TImings
The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms
generated are shown in Figure 5.
14
V961PBC Data Sheet Rev 2.4
Copyright © 1998, V3 Semiconductor Inc.
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