V961PBC-40REVB2 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'V961PBC-40REVB2' PDF : 16 Pages View PDF
V961PBC
Table 16: Revision History (cont’d)
Revision
Number
Date
Comments and Changes
1. In Table 1, changed Draining Strategy to “3 or more words” from “4 or more
writes”.
2. In Table 3, changed Base Address 3 to Unimplemented.
3. In Table 5, changed “PAR” to “PAR”.
4. In Table 6, changed “SCL” to “SCL/PERR”.
5. In Table 6, changed SDA to “I/O4 from “O4”.
1.3
4/95
6. In Table 6, changed ROMCSx,LREQ, and ADS to “I/O4” from”O4” (device
dependent).
7. In Table 6, changed GREQ,LBREQ, and HOLD to “O4” from “I/O4” (device
dependent).
8. In Table 6, changed BURST and BLAST to “I/O4” from “O4” (device depen-
dent).
9. In Table 6, changed ERR and BTERM to “I/O4” from “O4” (device dependent).
10. In Table 14, added timings for 16MHz and 40MHz (device dependent).
First released version of the data sheet. Some changes to AC and DC specifica-
1.2
3/95 tions and to waveforms. All future changes to the data sheet will be documented
in detail in this section.
1.1
2/95
Clean pinouts. Some DC and AC specs. Sent only to a limited number of cus-
tomers.
1.0
1/95
First pre-silicon revision of preliminary data sheet. DC and AC specs TBD. Sent
only to a limited number of customers.
16
V961PBC Data Sheet Rev 2.4
Copyright © 1998, V3 Semiconductor Inc.
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