VIS
Preliminary
Figure 23. Random Row Read (lnterleaving Banks)
(Burst Length = 2, CAS Latency = 1)
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS
t
CK1
Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto
Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
RAS
CAS
WE
DSF
BS
A9
RBu
RAu
RBv
RAv
RBw
RAW
RBx
RAx
RBy
RAy
RBz
RAz
A0 ~ A8
RBu CBu RAu CAu RBv CBv RAv CAv RBw CBw RAw CAw RBx CBx RAx CAx RBy CBy RAy CAy RBz CBz RAz
DQM
t RP
t RP
tRP
t RP
t RP
tRP
t RP
tRP
t RP
tRP
DQ
Bu0 Bu1 Au0 Au1 Bv0 Bv1 Av0 Av1 Bw0 Bw1 Aw0 Aw1 Bx0 Bx1 Ax0 Ax1 By0 By1 Ay0 Ay1 Bz0
Activate Activate
Command Command
Bank B
Bank A
Activate Activate
Command Command
Bank B
Bank A
Activate Activate
Command Command
Bank B
Bank A
Activate
Command
Bank B
Activate Activate
Command Command
Bank A
Bank B
Activate
Command
Bank A
Activate Activate
Command Command
Bank B
Bank A
Read
Bank B
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Read
Bank A
With Auto
Precharge
Read
Bank B
With Auto
Precharge
Document:1G5-0145
Rev.1
Page 75