VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
Figure 24. Full Page Random Column Read (Burst Length = Full Page, CAS Latency = 2)
CLK
CKE
CS
RAS
CAS
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
WE
DSF
BS
A9
RAx
RBx
RBw
A0 ~ A8
DQM
DQ
RAx
RBx CAx CBx CAy
CBy
CAz
CBz
RBw
tRP
tRRD
tRCD
Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2
Activate
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Read
Command Command
Bank B Bank A
Read
Read
Command Command
Bank A Bank A
Read
Command
Bank B
Precharge
Command Bank B
(Precharge Termination)
Activate
Command
Bank B
Document:1G5-0145
Rev.1
Page 76